vishay siliconix SI2323DDS document number: 64004 s13-1165-rev. a, 13-may-13 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com p-channel 20-v (d-s) mosfet features ? trenchfet ? power mosfet ?100 % r g tested ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? load switch ? pa switch ? dc/dc converters ? power management notes: a. surface mounted on 1" x 1" fr4 board. b. t = 5 s. c. maximum under steady stat e conditions is 175 c/w. d. t c = 25 c. product summary v ds (v) r ds(on) ( ? ) max. i d (a) d q g (typ.) - 20 0.039 at v gs = - 4.5 v - 5.3 13.6 nc 0.050 at v gs = - 2.5 v - 4.7 0.075 at v gs = - 1.8 v - 3.8 ordering information: SI2323DDS-t1-ge3 (lead (pb)-free and halogen-free) g to-236 (sot-23) s d top view 2 3 1 * marking code SI2323DDS (e4)* s g d p-channel mosfet absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 20 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) t c = 25 c i d - 5.3 a t c = 70 c - 4.3 t a = 25 c - 4.1 a,b t a = 70 c - 3.2 a,b pulsed drain current (t = 300 s) i dm - 20 continuous source-drain diode current t c = 25 c i s - 1.4 t a = 25 c - 0.8 a,b maximum power dissipation t c = 25 c p d 1.7 w t c = 70 c 1.1 t a = 25 c 0.96 a,b t a = 70 c 0.62 a,b operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, c t ? 5 s r thja 100 130 c/w maximum junction-to-foot (drain) steady state r thjf 60 75
vishay siliconix SI2323DDS www.vishay.com 2 document number: 64004 s13-1165-rev. a, 13-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 20 v v ds temperature coefficient ? v ds /t j i d = - 250 a - 13 mv/c v gs(th) temperature coefficient ? v gs(th) /t j - 2.8 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.4 - 1 v gate-source leakage i gss v ds = 0 v, v gs = 8 v 100 na zero gate voltage drain current i dss v ds = - 20 v, v gs = 0 v - 1 a v ds = - 20 v, v gs = 0 v, t j = 55 c - 10 on-state drain current a i d(on) v ds ?? - 5 v, v gs = - 4.5 v - 15 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 4.1 a 0.032 0.039 ? v gs = - 2.5 v, i d = - 2 a 0.041 0.050 v gs = - 1.8 v, i d = - 1 a 0.058 0.075 forward transconductance a g fs v ds = - 10 v, i d = - 4.1 a 18 s dynamic b input capacitance c iss v ds = - 10 v, v gs = 0 v, f = 1 mhz 1160 pf output capacitance c oss 135 reverse transfer capacitance c rss 120 total gate charge q g v ds = - 10 v, v gs = - 8 v, i d = - 4.1 a 24 36 nc total gate charge q g v ds = - 10 v, v gs = - 4.5 v, i d = - 4.1 a 13.6 21 gate-source charge q gs 2 gate-drain charge q gd 2.2 gate resistance r g f = 1 mhz 2 10 20 ? tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 3.1 ? i d ? - 3.2 a, v gen = - 4.5 v, r g = 1 ? 24 36 ns rise time t r 22 40 turn-off delay time t d(off) 52 78 fall time t f 11 20 tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 3.1 ? i d ? - 3.2 a, v gen = - 8 v, r g = 1 ? 816 rise time t r 918 turn-off delay time t d(off) 58 87 fall time t f 918 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - 1.4 a pulse diode forward current i sm - 20 body diode voltage v sd i s = - 3.2 a, v gs = 0 v - 0.79 - 1.2 v body diode reverse recovery time t rr i f = - 3.2 a, di/dt = 100 a/s, t j = 25 c 14 25 ns body diode reverse recovery charge q rr 612nc reverse recovery fall time t a 8 ns reverse recovery rise time t b 6
vishay siliconix SI2323DDS document number: 64004 s13-1165-rev. a, 13-may-13 www.vishay.com 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current and gate voltage gate charge 0 5 10 15 20 0 0.5 1 1.5 2 i d - drain current (a) v ds - drain-to-source voltage (v) v gs = 5 v thru 2.5 v v gs = 1.5 v v gs = 2 v v gs = 1.8 v 0.00 0.02 0.04 0.06 0.08 0.10 0 5 10 15 20 r ds(on) - on-resistance () i d - drain current (a) v gs = 1.8 v v gs = 2.5 v v gs = 4.5 v 0 2 4 6 8 0 7 14 21 28 v gs - gate-to-source voltage (v) q g - total gate charge (nc) v ds = 5 v v ds = 10 v v ds = 16 v i d = 4.1 a transfer characteristics capacitance on-resistance vs. junction temperature 0 1 2 3 4 5 0 0.5 1 1.5 2 i d - drain current (a) v gs - gate-to-source voltage (v) t c = 25 c t c = 125 c t c = - 55 c 0 500 1000 1500 2000 0 5 10 15 20 c - capacitance (pf) v ds - drain-to-source voltage (v) c iss c oss c rss 0.7 0.9 1.1 1.3 1.5 - 50 - 25 0 25 50 75 100 125 150 r ds(on) - on-resistance (normalized) t j - junction temperature ( c) v gs = 1.8 v, 1 a v gs = 2.5 v, 2 a v gs = 4.5 v, 4.1 a
vishay siliconix SI2323DDS www.vishay.com 4 document number: 64004 s13-1165-rev. a, 13-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage 0.1 1 10 100 0.0 0.3 0.6 0.9 1.2 i s - source current (a) v sd - source-to-drain voltage (v) t j = 150 c t j = 25 c 0.3 0.45 0.6 0.75 0.9 - 50 - 25 0 25 50 75 100 125 150 v gs(th) (v) t j - temperature ( c) i d = 250 a on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0 0.02 0.04 0.06 0.08 0.1 1 2 3 4 5 r ds(on) - on-resistance () v gs - gate-to-source voltage (v) t j = 125 c t j = 25 c i d = 4.1 a 0 10 20 30 0.001 0.01 0.1 1 10 100 time (s) po w er ( w ) safe operating area, junction-to-ambient 0.01 0.1 1 10 100 0.1 1 10 100 i d - drain current (a) v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specified 100 ms limited by r ds(on) * 1 ms t a = 25 c bvdss limited 10 ms 100 s 1 s, 10s dc
vishay siliconix SI2323DDS document number: 64004 s13-1165-rev. a, 13-may-13 www.vishay.com 5 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) * the power dissipation p d is based on t j(max.) = 150 c, using junction-to-cas e thermal resistance, and is mo re useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0 1.5 3 4.5 6 0 25 50 75 100 125 150 i d - drain current (a) t c - case temperature ( c) power derating, junction-to-foot 0 0.5 1 1.5 2 0 25 50 75 100 125 150 power (w) t c - case temperature ( c) power, junction-to-ambient 0 0.18 0.36 0.54 0.72 0.9 0 25 50 75 100 125 150 power (w) t a - ambient temperature ( c)
vishay siliconix SI2323DDS www.vishay.com 6 document number: 64004 s13-1165-rev. a, 13-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64004 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 s qu are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja =175 c/ w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 single p u lse 0.02 0.05 normalized thermal transient impedance, junction-to-foot 1 0.1 0.01 d u ty cycle = 0.5 s qu are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 10 -3 10 -2 1 10 -1 10 -4 0.02 single p u lse 0.1 0.2 0.05
vishay siliconix package information document number: 71196 09-jul-01 www.vishay.com 1 sot-23 (to-236): 3-lead b e e 1 1 3 2 s e e 1 d a 2 a a 1 c s e a ting pl a ne 0.10 mm 0.004" c c l 1 l q g au ge pl a ne s e a ting pl a ne 0.25 mm dim millimeters inches min max min max a 0.89 1.12 0.0 3 5 0.044 a 1 0.01 0.10 0.0004 0.004 a 2 0.88 1.02 0.0 3 46 0.040 b 0. 3 5 0.50 0.014 0.020 c 0.085 0.18 0.00 3 0.007 d 2.80 3 .04 0.110 0.120 e 2.10 2.64 0.08 3 0.104 e 1 1.20 1.40 0.047 0.055 e 0.95 bsc 0.0 3 74 ref e 1 1.90 bsc 0.0748 ref l 0.40 0.60 0.016 0.024 l 1 0.64 ref 0.025 ref s 0.50 ref 0.020 ref q 3 8 3 8 ecn: s-0 3 946-rev. k, 09-jul-01 dwg: 5479
an807 vishay siliconix document number: 70739 26-nov-03 www.vishay.com 1 mounting little foot sot-23 power mosfets wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ), for the basis of the pad design for a littl e foot sot-23 power mosfet footprint . in converting this footprint to the pad set for a power device, designers must make tw o connections: an electrical connection and a thermal connection, to draw heat away from the package. the electrical connections for the sot-23 are very simple. pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. as in the other little foot packages, the drai n pin serves the additional function of providing the thermal connection from the package to the pc board. the total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. also, heat spreads in a circular fashion from the heat source. in this case the drain pin is the heat source when looking at heat spread on the pc board. figure 1 shows the footprint with copper spreading for the sot-23 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copper over lies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the ambient air. this pattern uses all the available area underneath the body for this purpose. figure 1. footprint with copper spreading 0.114 2.9 0.059 1.5 0.0394 1.0 0.037 0.95 0.150 3.8 0.081 2.05 since surface-mounted packages are small, and reflow soldering is the most common way in whic h these are affixed to the pc board, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device.
application note 826 vishay siliconix document number: 72609 www.vishay.com revision: 21-jan-08 25 application note recommended minimum pads for sot-23 0.106 (2.692) recommended mi nimum pads dimensions in inches/(mm) 0.022 (0.559) 0.049 (1.245) 0.029 (0.724) 0.037 (0.950) 0.053 (1.341) 0.097 (2.459) return to index return to index
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